APEX-SZ Array Wedge Fabrication Steps

11-3-03

Jared Mehl

 

Note:  Unresolved issues in Bold!

 

1)      Order 150 μm thick silicon wafers, double-side polished (less prone to breakage).  Currently we are getting our wafers from Silicon Quest International, Inc. 

2)       Clean wafers in sink6 (piranha bath only, no HF necessary, resistance meter has to read > 10 M-Ohm).  Put in spin dryer srd to rinse and dry wafers; currently its dirty so the red bars won’t go all the way to the top, but that’s OK (according to Jimmy Chang).

3)      Low stress silicon nitride deposition in tystar17 furnace.  Deposit 1 μm of Si3N4 using recipe LSNSTDA.017.  Lately the deposition rate has been ~40 Å/min, so we have been using 4 hours, 10 minutes of deposition time.

4)      Give wafers to Xiaofan Meng to have him deposit 2000 Å of Niobium and 1000-1500 Å SiO2 to form superconducting ground plane for lead wiring.  These numbers are not fixed and really aren’t very critical as long as the ground plane is isolated and superconducting.

5)      Sputter Aluminum / Titanium bilayer for thermistor in cpa.  We use 1.0 kW power and one pass @ 40.0 cm/min to get 400 Å of Al, and 1.5 kW power and 2 passes @ 31.3 cm/min to get 800 Å of Ti.  Be sure to wait few minutes between passes for palette to cool off.   The above parameters will give a Tc ~ 520 mK (as of Jan 03) and RN ~ 1.8 Ω for the thermistor (as of Jan 2003 testing). 

6)      Ti photolithography step.  Standard lithography is:

a)      HMDS in primeoven using setting “1”  (using “0” is OK too).

b)     Deposit ~1.1 μm I-line photoresist in svgcoat1/2; spin station program “1” and oven station program “1” (60s bake at 60 C).

c)      Expose in gcaws, running a focus/exposure test on a dummy first (for critical thermistor steps at least).  Recently we have been using 5-6 s exposure times (exact number not that critical) and whatever the posted focus value is.  Shrink aperture to 9 mm x 9 mm by setting the dials to 7.5 (10 divisions) on all sides.  For Ti layer, there are 3 steps: program ALIGN with ‘APEX ALIGN’ mask to put down alignment marks, use program HEX, passes 1 and 2 (need to write another pass onto the HEX program or new program for witness samples!), and mask APEX TI to put down thermistors, and finally use blank mask and pass 3 to get Ti off of contact pads.  Normal layers will usually just require you run program HEX (1&2) with the appropriate mask plus witness sample program.

d)     Develop resist with svgdev, post-exposure bake (PEB) first (spinner station “8”, oven station “1”), then develop normally (spinner “1”, oven “7”).

7)      Etch Titanium layer in ptherm. Be sure to turn on cooling water (has to be done separately from enabling machine).  Clean chamber first with O2 plasma at 200 W and 100 sccm for 15 minutes, followed by SF6 at 200 W and 100 sccm for 5 minutes (to get rid of any residual oxygen? This is what Xiaofan does).  Place wafer into etch chamber on top of aluminum wafer holder.  Then etch with SF6 at 200 W and 100 sccm for 2.5 minutes (etch stops on Al anyways).

8)      Standard PR clean: 

a)      Soak wafer in acetone bath until PR dissolves off

b)     Rinse quickly with isopropanol (into acetone bath)

c)      Rinse quickly with DI water.

d)     Use air gun to blow dry.

9)      Aluminum photolithography, see step #6, with following exceptions: Bake for 90s in svgcoat to harden PR further and avoid mask sticking to wafer in ksaligner.  Use APEX AL (???) for first two passes of program, and use old AL mask with contact pads for witness samples (WS), this mask must be rotated 90˚ CCW when placing in gcaws.  Don’t do developer step yet!

10)  Lead wiring lithography in ksaligner.   ‘Contact WS’ mask.  Use following parameters: Soft contact mode, 6.0s exposure time, and alignment gap 50 μm.  Now develop (with PEB first) as in step #5 in svgdev.

11)  Etch aluminum in lam3.  Run 3 dummies first.  Use standard program (loaded from cartridge) with following modifications: In Reactor #2 change to COMPL:TIME and WAIT:00:25s.  Set Reactor #3 (overetch) 00%.  Set Airlock #1 to 00:30s.

12)  Ash photoresist in technics-c.  O2 plasma at 300 W power and 51.7 sccm for 7 minutes.

13)  Groundplane lithography step, same as #5 but using GROUND PLANE mask.

14)   Etch Nb and SiO2 somehow, either in ptherm or have Xiaofan do it!?!.

15)  Remove PR, probably a la step #8.

16)  “Thin” gold photolithography: Standard liftoff lithography step:

a)      HMDS in primeoven using setting “1” (or “0” ok)

b)     Deposit ~1.1 μm I-line photoresist in svgcoat1/2; spin station program “1” and oven station program “1” (60s bake at 60 C)

c)      Developer pre-soak in svgdev to harden top of PR layer for liftoff: spin station program “1” (60s developer soak & rinse), and oven program “7” (nothing)

d)     Expose in gcaws as in step #5 but with ‘AU WEB WS’ mask (better test structures than old mask)

e)      Develop in svgdev, PEB with spin station “8” oven station “1” followed by develop spin station “1” and oven station “7”

17)  ”Thin” gold deposition in v401 (veeco).  Check out gold wire from Microlab office.  Clean boats and wire (appropriately cut and twisted to small bundles) in acetone 3-5 minutes in ultrasonic bath, then rinse with isopropanol, and blow dry with air gun.  In veeco, deposit ~20 Å Ti first (helps Au stick) then deposit ~250 Å of Au, as measured on crystal monitor (saw evidence of absorption for >200 Å).  Absorption still needs to be tested optically!

18)  Liftoff step: let wafer sit in acetone bath until all resist comes off with gold layer.  Has to sit a few hours at least; better if left overnight.  Also may need to stick it in ultrasound bath for a few minutes to shake off rest of resist.  Rinse wafer with isopropanol, DI water, and blow dry as before.  Dump resulting solution in red acetone/PR buckets in old lab.

19)  “Thick” gold photolithography: liftoff lithography as in step #16 but use ‘AU Lead WS’ mask.

20)  “Thick” gold deposition in v401 (veeco).  Clean gold as in step #17.  Deposit ~ 20 Å Ti for stickiness, and then ~600-700 Å of Au (as measured on crystal monitor, check in alphastep to get actual thickness).  This is our best guess at getting G ~ 2e-10 W/K, but still needs to be checked!

21)  Liftoff as in step #18.

22)  Nitride photolithography step: same as step #5, except use ~2 μm of photoresist (spin program “5” and oven program “2” on svgcoat1/2), and use mask ‘APEX Nitride’.

23)  Etch Si3N4 in ptherm.  Clean chamber first as in step #7.  Also use custom aluminum wafer holder.  Etch with SF6 at 200 W with 100.0 sccm for roughly 1 minute / 1000 Å of Si3N4 (i.e. 10 minutes for 1 μm, check thickness with nanospec).  Note: don’t clean off PR afterwards!

24)  Cut out wedge in disco.  There are aluminum guidelines to cut along, make sure blade actually cuts to the inside (towards wedge) of these lines, which are 50 μm thick.  Still need to figure out way to robustly remove thin wafers from blue sticky tape!

25)  Release spiderwebs in xetch.  Current recipe: 4 Torr XeF2 and 3 Torr N2 at 45 seconds / cycle for 100 cycles.  Note that it will take slightly more than 5 hours to finish the recipe.

26)  Final PR ash in ptherm.  Use O2 plasma at 200 W power with 100.0 sccm flow for 7 minutes.

27)  Enjoy your new APEX-SZ bolometer array wedge!